Virtually all complex integrated circuits are designed with the use of computer aided design (CAD) tools. Some CAD tools, called simulators, help the circuit designer verify the operation of a proposed circuit. Another type of CAD tool, called a silicon compiler, generates the semiconductor mask patterns (herein called the circuit layout) from a detailed circuit specification.
The present invention concerns a new type of computer aided design tool--one which helps circuit designers determine the size and layout floor plan of a circuit well before the details of the circuit have been determined or designed.
The inventor has coined this new tool a "synthetic netlist generator".
More particularly, referring to FIG. 1, the present invention 20 generates a "synthetic netlist" 22 (i.e., a kind of "pseudo circuit"), which mimics the characteristics of a specified "target circuit" and is suitable for use with a silicon compiler 24. The silicon compiler 24 combines the synthetic netlist 22 with a specified or predefined floor plan 26 to generate a layout 28 which will have approximately the same size and interconnection complexity as the specified target circuit. The detailed circuit specification used by silicon compilers and circuit simulators is often called a netlist, and comprises a list of circuit components and the interconnections between those components. A netlist for the circuit shown in FIG. 2 is shown in Table 1.
TABLE 1 ______________________________________ Exemplary Netlist Name of Cell Input Signals Output Signals Instance Name 1 2 3 1 2 3 ______________________________________ S1 XOR A B C S2 XOR C CN1 S A1 AND A B CA A2 AND C CN1 CB R NOR CB CA CN ______________________________________
The netlist defines all of the interconnections between the components of the circuit. Each "signal" which interconnects two or more cells, or which represents an input or output for the entire circuit, is actually a node in the circuit which has been assigned a name. Thus the terms "signal" and "node" are often used interchangeably.
In addition, the netlist specifies the nature of its components by specifying a cell name for each component. The cell name, in turn, specifies or points to a particular circuit in a predefined library of cells.
The problem that the present invention solves is as follows. The most important characteristic affecting the cost of manufacturing any integrated circuit is its size--i.e., the size of the circuit's layout. As a result, circuit designers are intensely interested in determining or estimating the size of the circuits that they are designing before they actually embark on the task of designing the details of the circuit. The reason for this is quite simple: if the circuit will be too large or expensive to manufacture, it is best to know that as soon as possible so that the specification for the circuit can be changed, or the product abandoned before resources have been wasted on an ill conceived product.
Circuit designers are also interested in seeing how different "floor plans" (i.e., schemes for arranging the major components and signal lines of a circuit) affect the size and utilization of the space occupied by any particular circuit before the circuit is designed. The synthetic netlist generated by the present invention is very useful in the "floor planning" process because it enables the circuit designer to test different potential floor plans and thereby select the best floor plan for a specified circuit. The information obtained from such preliminary studies can also change how the circuit will be designed and may even affect the decision as to which features will and will not be included in a particular circuit.
The prior art methods for estimating the size and complexity of a specified target circuit are quite primitive. Generally, these involve the use of very rough "rules of thumb" for scaling up or down the size of a previously designed circuit. In contrast, the present invention enables a relatively precise analysis of a specified target circuit.